NVTS Is Quietly Collapsing the AI Power Delivery Stack

Navitas Semiconductor is still widely described as a gallium nitride (GaN) power chip company. That framing is increasingly outdated. What Navitas is actually doing is subtler and more consequential. It is shifting from a power chip supplier toward an architecture owner by redefining how power is delivered inside AI systems.

That distinction matters because, in AI power delivery, value does not accrue to whoever supplies the most chips. It accrues to whoever defines the architecture, especially as energy, rather than compute, becomes the binding constraint on AI system performance.

NVTS is not a component vendor

Currently, at the GPU adjacent power chip level, power chip companies sell discrete power chips; a switch here, a controller there, protection somewhere else. The system integrator then assembles those discrete power chips into a multistage power delivery stack, where each additional conversion step and interconnect introduces inherent energy losses.

To address these energy losses, Navitas adopted an integrated architecture strategy. Its gallium nitride (GaN) based power chips integrate multiple power functions, including switching, control, sensing, and protection, into a single power chip optimized for efficiency. This integration replaces multiple discrete power chips with a single power chip, shifting more design responsibility away from the system integrator and into Navitas’ integrated architecture.

Architecture expansion into SiC

Navitas is now using its same integrated architecture upstream at the rack level to condition electricity before it reaches the GPU adjacent GaN power chip, where silicon carbide (SiC) is used. While Navitas has not yet detailed a fully integrated SiC power chip equivalent to its GaN power chip, the company has indicated that its integration first discipline is being applied across higher voltage SiC domains.

GaN power chips operate closest to the GPU, where power delivery and switching speed matter most. SiC power chips operate upstream, conditioning higher voltage power before feeding those GPU adjacent GaN power chips. Together, these form NVTS’s integrated GaN and SiC power delivery architecture, which controls how power moves through the stack from rack to GPU more efficiently than discrete power chips and workaround architectures like packaged power chips.

Collapsing the power delivery stack

Collapsing the power delivery stack is primarily about improving system level efficiency through integration, while GaN and SiC enable optimized GPU compute through superior power handling and faster switching. It is not just about offering both GaN and SiC power chips. It requires reducing what has historically been a multistage architecture into fewer, tightly integrated power chips that improve efficiency across the full power delivery stack. By combining integration with advanced materials, NVTS can deliver more usable compute from the same power budget, but those material advantages ultimately serve the primary objective of improving system level efficiency through integration.

Architecture ownership creates the moat

Navitas’s moat comes from its integrated GaN and SiC power delivery architecture, which enables a collapsed power delivery stack across voltage domains. By combining integration of control, switching, sensing, and protection inside a single power chip with chip material choice, NVTS delivers gains in power efficiency and GPU compute performance across the stack that cannot be matched by swapping discrete power chips, even if they use the same materials.

Why this matters now for AI and data centers

Navitas’s power delivery architecture becomes critical as AI data centers face system level power stress. GaN power chips solve power delivery closest to the GPU, but they do not remove the constraint if upstream rack level power remains inefficient. As AI racks scale, conversion and distribution losses in rack power increasingly erode the performance gains GaN enables at the GPU. This shifts the choke point upstream, making optimization of higher voltage SiC power chips essential and turning a collapsed power delivery architecture from a design preference into a system requirement.

Risks and failure modes

None of this is guaranteed. Hyperscalers may choose to internalize more of the power delivery stack over time. Execution in SiC is capital intensive and highly competitive, and adoption timelines may lag optimistic AI capex narratives. Incumbent power chip vendors still benefit from scale, manufacturing depth, and entrenched customer relationships.

Most importantly, collapsing the power delivery stack only works if customers prioritize simplification and system efficiency over modular, multivendor optionality. If the market ultimately prefers flexibility to architectural consolidation, Navitas’s leverage diminishes. These risks are real, but they are also the unavoidable cost of pursuing architecture ownership rather than remaining a discrete power chip supplier.

Closing frame

By spanning GPU adjacent GaN and upstream SiC, and applying the same integration discipline across voltage domains, Navitas is no longer competing on incremental efficiency curves. It is defining how power moves through AI systems. That shift quietly repositions where value accrues in the power delivery stack. The payoff is not immediate returns, but structural dependence. In power electronics, that is how category defining businesses are built.

Disclosure: This article reflects the author’s personal analysis and opinions and is not investment advice. The author holds shares in Navitas Semiconductor (NVTS) at the time of writing. Images used are independent illustrative renderings and are not official Navitas Semiconductor promotional materials.

RISK PROFILE
Architecture Adoption: NVTS’s integrated GaN and SiC power delivery architecture depends on hyperscalers prioritizing system level efficiency over discrete, multivendor flexibility. If customers internalize power design or favor discrete power chips, NVTS may see slower adoption of its integrated architecture.