NVTS Is Quietly Collapsing (and Owning) the AI Power Delivery Stack

Navitas Semiconductor is still widely described as a gallium nitride (GaN) power chip company. That framing is increasingly outdated. What Navitas is actually doing is subtler and more consequential. It is shifting from a power chip supplier toward an architecture owner by redefining how power is delivered inside AI systems.

That distinction matters because, in AI power delivery, value does not accrue to whoever supplies the most chips. It accrues to whoever defines the architecture, especially as energy, rather than compute, becomes the binding constraint on AI system performance.

NVTS is not a component vendor

Currently, aside from Navitas, power chip companies sell discrete power chips; a switch here, a controller there, protection somewhere else. The system integrator then assembles those discrete power chips into a power delivery stack with inherent efficiency losses.

To address this energy constraint, Navitas took a different path early. Its gallium nitride based power chips integrate multiple power functions; switching, control, sensing, and protection into a single power chip optimized for efficiency. This integration collapses what had been separate power functions at the chip level, shifting responsibility away from the system integrator and toward Navitas, which now defines the internal architecture of the GPU adjacent power chip.

Architecture expansion into SiC

The same integration architecture that collapsed power functions into a single GaN power chip is now being extended upstream into the power delivery stages that condition electricity before it reaches the GPU, where silicon carbide (SiC) is used.

GaN operates closest to the GPU, where fast switching and power density matter most. SiC operates upstream, conditioning higher-voltage power before feeding those GPU adjacent GaN power chips. Together, this forms NVTS’s unified GaN and SiC power chip architecture, which controls how power moves through the stack from rack to GPU more efficiently than discrete power chips and board level workaround designs.

Collapsing the power delivery stack

Collapsing the power delivery stack is not just about offering both GaN and SiC power chips. It requires reducing what has historically been a multistage system into fewer, tightly integrated power chips that deliver more usable compute from the same power budget. This is precisely what NVTS is positioned to accomplish as it prepares to roll out integrated SiC power chips alongside its GaN power chips.

Traditional power delivery stacks fail to deliver this outcome because they are fragmented by design and not optimized for efficiency across the full power delivery stack. Each discrete power function introduces power delivery losses and slower switching speeds. Those losses do not show up on a power bill. They show up as lost GPU performance.

Architecture ownership creates the moat

Navitas’s moat comes from its integrated GaN and SiC power chip design, which enables a collapsed power delivery stack across voltage domains. By combining chip material choice with integration including control, switching, sensing, and protection inside a single power chip, NVTS delivers gains in power efficiency, switching behavior, and performance headroom across the stack that cannot be matched by swapping discrete power chips, even when individual components remain competitive.

Why this matters now for AI and data centers

Navitas’s power delivery stack architecture becomes critical as AI data centers face system level power stress. GaN power chips solve power delivery closest to the GPU, but they do not remove the constraint if upstream rack-level power remains inefficient. As AI racks scale, conversion and distribution losses in rack power increasingly erode the performance gains GaN enables at the GPU. This shifts the choke point upstream, making optimization of higher-voltage SiC power chips essential and turning a collapsed, architecture driven power delivery stack from a design preference into a system requirement.

Risks and failure modes

None of this is guaranteed. Hyperscalers may choose to internalize more of the power delivery stack over time. Execution in SiC is capital intensive and highly competitive, and adoption timelines may lag optimistic AI capex narratives. Incumbent power chip vendors still benefit from scale, manufacturing depth, and entrenched customer relationships.

Most importantly, collapsing the power delivery stack only works if customers prioritize simplification and system efficiency over modular, multivendor optionality. If the market ultimately prefers flexibility to architectural consolidation, Navitas’s leverage diminishes. These risks are real, but they are also the unavoidable cost of pursuing architecture ownership rather than remaining a component supplier.

Closing frame

By spanning GPU adjacent GaN and upstream SiC, and applying the same integration discipline across voltage domains, Navitas is no longer competing on incremental efficiency curves. It is defining how power moves through AI systems. That shift quietly repositions where value accrues in the power delivery stack. The payoff is not immediate returns, but structural dependence. In power electronics, that is how category defining businesses are built.

Disclosure: This article reflects the author’s personal analysis and opinions and is not investment advice. The author holds shares in Navitas Semiconductor (NVTS) at the time of writing. Images used are independent illustrative renderings and are not official Navitas Semiconductor promotional materials.

RISK PROFILE
Architecture driven gains depend on customer adoption, successful SiC execution, and market preference for integrated power stacks over modular designs.